Anti-fuse repair control circuit and semiconductor device including DRAM having the same
US7688663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Apr 6, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2229/763
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.