Semiconductor device with improved power supply control for a plurality of memory arrays
US7688670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2008 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Jul 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.