Integrated circuit and method for identifying propagation time errors in integrated circuits
US7689885B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Jan 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318544
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit is disclosed. In one embodiment, for each clock domain there is at least one clock driver which is situated in the integrated circuit and which drives circuits situated in the clock domain. Each clock driver in the clock domain contains a clock input and an enable input, and its output outputs the clock received at the clock input if an enable signal is applied to the enable input. The clock driver receives a clock derived from the signal at the functional clock input, and the enable signal is connected in line with the values stored in the signal sequence registers if there is a signal change at the scan clock input when the scan chain shift mode has been switched off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.