Write margin calculation tool for dual-port random-access-memory circuitry
US7689941B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Jun 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.