Increased power line noise immunity in IC using capacitor structure in fill area
US7689961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2005 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Jun 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Increase power line noise immunity in an IC is provided by using decoupling capacitor structure in an area of the IC that is typically not used for routing, but filled with unconnected and non-functional metal squares (fills). In one embodiment, a method includes providing a circuit design layout; determining a density of a structure in an area of the circuit design layout; and in response to the density being less than a pre-determined density for the structure in the area, filling in a portion of the area with at least one capacitor structure until a combined density of the structure and the at least one capacitor structure in the area is about equal to the pre-determined density. Power line noise immunity is increased by increasing decoupling capacitance without enlarging the IC's total size by using a (fill) area that would normally be filled with unconnected and non-functional metal shapes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.