Use of step and flash imprint lithography for direct imprinting of dielectric materials for dual damascene processing

US7691275B2 · kind B2 · utility

Assignee

• The Board of Regents of the University of Texas System · US

Inventors

• C. Grant Willson · Austin, US
• Frank L. Palmieri · Hampton, US
• Yukio Nishimura · Tokyo, JP
• Stephen C. Johnson · Fullerton, US
• Michael Stewart · Toronto, CA

Key dates

• Filing date: Feb 27, 2006
• Grant date: Apr 6, 2010
• Expiry date: Mar 13, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76828
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In some embodiments, the present invention is directed to methods that involve the combination of step-and-flash imprint lithography (SFIL) with a multi-tier template to simultaneously pattern multiple levels of, for example, an integrated circuit device. In such embodiments, the imprinted material generally does not serve or act as a simple etch mask or photoresist, but rather serves as the insulation between levels and lines, i.e., as a functional dielectric material. After imprinting and a multiple step curing process, the imprinted pattern is filled with metal, as in dual damascene processing. Typically, the two printed levels will comprise a “via level,” which is used to make electrical contact with the previously patterned under-level, and a “wiring level.” The present invention provides for the direct patterning of functional materials, which represents a significant departure from the traditional approach to microelectronics manufacturing.