Method for fabricating silicon carbide vertical MOSFET devices
US7691711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2008 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Oct 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
Abstract
A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.