Inventor · Delmar, NY, US

Jody A. Fronheiser

49Patents

10h-index

67Co-inventors

74Inventor score

Filing activity: Aug 23, 2006 → Jun 6, 2019

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9343300B1	Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region	Electricity	24	Active
US8673718B2	Methods of forming FinFET devices with alternative channel materials	Electricity	22	Active
US8728885B1	Methods of forming a three-dimensional semiconductor device with a nanowire channel structure	Electricity	20	Active
US9165837B1	Method to form defect free replacement fins by H2 anneal	Electricity	20	Active
US8580642B1	Methods of forming FinFET devices with alternative channel materials	Electricity	19	Active
US9362405B1	Channel cladding last process flow for forming a channel region on a FinFET device	Electricity	13	Active
US7691711B2	Method for fabricating silicon carbide vertical MOSFET devices	Electricity	13	Active
US7850941B2	Nanostructure arrays and methods for forming same	Emerging Cross-Sectional Technologies	13	Active
US9224865B2	FinFET with insulator under channel	Electricity	11	Active
US9117875B2	Methods of forming isolated germanium-containing fins for a FinFET semiconductor device	Electricity	11	Active
US9716174B2	Electrical isolation of FinFET active region by selective oxidation of sacrificial layer	Electricity	9	Active
US9236452B2	Raised source/drain EPI with suppressed lateral EPI overgrowth	Electricity	7	Active
US7595241B2	Method for fabricating silicon carbide vertical MOSFET devices	Electricity	6	Active
US9245980B2	Methods of forming substantially defect-free, fully-strained silicon-germanium fins for a FinFET semiconductor device	Electricity	5	Active
US8853019B1	Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process	Performing Operations; Transporting	5	Active
US8815685B2	Methods for fabricating integrated circuits having confined epitaxial growth regions	Electricity	4	Active
US9324790B2	Self-aligned dual-height isolation for bulk FinFET	Electricity	4	Active
US9647086B2	Early PTS with buffer for channel doping control	Electricity	4	Active
US9564486B2	Self-aligned dual-height isolation for bulk FinFET	Electricity	4	Active
US9478663B2	FinFET device including a uniform silicon alloy fin	Electricity	3	Active
US9530869B2	Methods of forming embedded source/drain regions on finFET devices	Electricity	3	Active
US9882052B2	Forming defect-free relaxed SiGe fins	Electricity	2	Active
US9508848B1	Methods of forming strained channel regions on FinFET devices by performing a heating process on a heat-expandable material	Electricity	2	Active
US7906427B2	Dimension profiling of SiC devices	Emerging Cross-Sectional Technologies	1	Active
US9508853B2	Channel cladding last process flow for forming a channel region on a FinFET device having a reduced size fin in the channel region	Electricity	1	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.