Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor
US7691714B2 · kind B2 · utility
3Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2005 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Jan 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.