Phase-changeable memory devices including an adiabatic layer
US7692176B2 · kind B2 · utility
3Cited by
13References
15Claims
0Family size
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Key dates
| Filing date | Jul 29, 2005 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Jan 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.