Multiple dual bit memory integrated circuit system
US7692236B1 · kind B1 · utility
2Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2005 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Feb 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
Abstract
A multiple dual bit integrated circuit system is provided that includes forming first address lines in a semiconductor substrate and forming a charge-trapping layer over the semiconductor substrate. A semiconductor layer is formed over the charge-trapping layer and second address lines are formed in the semiconductor layer to form a plurality of dual bit locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.