3-dimensional integrated circuit architecture, structure and method for fabrication thereof
US7692944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2008 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | May 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.