System and method for detecting multiple matches
US7694069B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2007 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Aug 13, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.