Structures and methods for low-k or ultra low-k interlayer dielectric pattern transfer
US7695897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2006 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Feb 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76813
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.