Method to manufacture LDMOS transistors with improved threshold voltage control
US7696049B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2006 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Jun 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A double diffused region (65), (75), (85) is formed in a semiconductor substrate or in an epitaxial layer (20) formed on the semiconductor substrate. The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to the hard bake process, a heavy implant species such as arsenic is implanted into the epitaxial layer. During subsequent processing, such as during LOCOS formation, a double diffused region is formed by a thermal anneal. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.