Method of fabricating a MOSFET having doped epitaxially grown source/drain region on recessed substrate
US7696051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2005 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Jul 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
Abstract
A MOSFET includes a semiconductor substrate with a first region having a relatively thick first thickness and a second region having a relatively thin second thickness; a gate insulating layer pattern formed on the first region of the semiconductor substrate; a gate conductive layer pattern formed on the gate insulating layer pattern; an epitaxial layer formed on the second region of the semiconductor substrate so as to have a predetermined thickness; spacers formed on sidewalls of the gate conductive layer pattern and part of the surface of the epitaxial layer; a lightly-doped first impurity region formed in the semiconductor substrate disposed below the spacers and in the epitaxial layer; and a heavily-doped second impurity region formed in a portion of the semiconductor substrate, exposed by the spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.