Semiconductor integrated circuit device and process for manufacturing the same
US7696608B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 30, 2007 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Jun 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.