Level shifter circuit incorporating transistor snap-back protection
US7696805B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2007 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Aug 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35613
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.