Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
US7696811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2007 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Dec 11, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.