Reducing programming error in memory devices
US7697326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2007 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | May 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/1332
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for storing data in an array (28) of analog memory cells (32) includes defining a constellation of voltage levels (90A, 90B, 90C, 90D) to be used in storing the data. A part of the data is written to a first analog memory cell in the array by applying to the analog memory cell a first voltage level selected from the constellation. After writing the part of the data to the first analog memory cell, a second voltage level that does not belong to the constellation is read from the first analog memory cell. A modification to be made in writing to one or more of the analog memory cells in the array is determined responsively to the second voltage level, and data are written to the one or more of the analog memory cells subject to the modification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.