Asynchronous multiple-order issue system architecture
US7698535B2 · kind B2 · utility
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35References
41Claims
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Key dates
| Filing date | Sep 16, 2003 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Sep 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous circuit is described for processing units of data having a program order associated therewith. The circuit includes an N-way-issue resource comprising N parallel pipelines. Each pipeline is operable to transmit a subset of the units of data in a first-in-first-out manner. The asynchronous circuit is operable to sequentially control transmission of the units of data in the pipelines such that the program order is maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.