Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renaming
US7698537B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2006 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Apr 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/481
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus processes a stream of instructions from an instruction set. The instruction set includes exception instructions and non-exception instructions. Exception instructions may cause a break in an instruction flow, and non-exception instructions execute in a statically determinable way. At least two processing blocks process instructions from the stream of instructions. A first processing block has a set of physical registers associated with it for storing data values being processed by the first processing block. Renaming circuitry associated with the first processing block maps architectural registers specified in instructions to be processed by the first processing block to physical registers within the set of physical registers. A second processing block has a set of physical registers associated with it for storing data values being processed by the second processing block. The second processing block and registers do not support renaming. Control circuitry identifies exception instructions in the instruction stream and detects when the exception instructions have been committed. The second processing block receives signals from the control circuitry and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.