Method of fabricating a vertical transistor and capacitor

US7700432B2 · kind B2 · utility

Assignee

• Agere Systems Inc. · US

Inventors

• Samir Chaudhry · Orlando, US
• Paul Arthur Layman · Schreiber, CA
• John Russell McMacken · Orlando, US
• J. Ross Thomson · Clermont, US
• Jack Qingsheng Zhao · Orefield, US

Key dates

• Filing date: Jan 9, 2009
• Grant date: Apr 20, 2010
• Expiry date: Jan 9, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/047

Abstract

A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.