Chip package carrier and fabrication method thereof
US7700986B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2008 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Nov 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09809
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package carrier is disclosed, which includes a first circuit layer, a second circuit layer, a core layer, a third circuit layer, a first dielectric layer between the first and third circuit layers, a fourth conductive layer including at least a solder ball pad, a second dielectric layer between the second and fourth circuit layers and at least a capacitor device, wherein the core layer has at least a first through-hole; the third circuit layer is disposed above the first circuit layer and includes at least a die pad; the capacitor device is disposed in the first through-hole. The capacitor device herein includes a first pillar electrode covering the wall of the first through-hole, a cylindrical capacitor material disposed in the first pillar electrode and having a first blind hole, and a second pillar electrode disposed in the first blind hole and connected to the die pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.