CMOS EPROM and EEPROM devices and programmable CMOS inverters
US7700993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2007 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Oct 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0195
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.