Single poly CMOS logic memory cell for RFID application and its programming and erasing method
US7700994B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2007 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Feb 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable/programmable CMOS logic memory cell for RFID applications and other mobile applications includes a tunneling capacitor, a control capacitor, and a CMOS inverter that share a single floating gate. A two-phase program/erase operation performs an initial Fowler-Nordheim (F-N) injection phase using the capacitors, and then a Band-to-Band Tunneling (BBT) phase using the CMOS inverter. Both the F-N injection and BBT phases are performed using low currents and low voltages (i.e., 5V or less). The tunneling and control capacitors are fabricated in isolated P-wells (IPWs) including both N+ and a P+ regions to enable the use of both positive and negative programming voltages during the F-N and BBT programming/erasing operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.