Method of producing a low-voltage power supply in a power integrated circuit
US7701006B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 9, 2009 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Jan 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
In a chip containing high-voltage device with a semiconductor substrate of a first conductivity type, a method of implementing low-voltage power supply is provided, wherein the electrical potential of an isolated region of a second conductivity type in a surface portion is used as one output terminal or as a voltage by which a transistor is controlled to provide output current for a low-voltage power supply. The other output terminal could be either terminal of the two that apply high voltage to high-voltage device or could be a floating terminal. Using this method, a low-voltage power supply can be implemented not only for the low-voltage integrated circuit (I) in a power IC containing one high-voltage device, but also for the low-voltage integrated circuit in a power IC having totem-pole connection or CMOS connection. As there is no need to implement depletion mode device in the chip, the fabrication cost is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.