Patent · US Active

Stacked die network-on-chip for FPGA

US7701252B1 · kind B1 · utility

101Cited by

0References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Francis Man-Chit Chow · San Jose, US
Rakesh Patel · Cupertino, US
Erhard Joachim Pistorius · Mountain View, US

Key dates

Filing date	Mar 3, 2008
Grant date	Apr 20, 2010
Priority date	—
Expiry date	Mar 3, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.