Method of arranging fuses in a fuse box of a semiconductor memory device and a semiconductor memory device including such an arrangement
US7701744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2007 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Jun 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device may include a memory cell array and at least one fuse box. The memory cell array may include a plurality of sub-array blocks, and a fuse box may include a plurality of fuse groups, each group corresponding to a sub-array block. Each fuse group may have a plurality of fuses, wherein the fuses are intermittently arranged such that fuses of the same fuse group are not adjacent to each other. Each fuse group may further include a master fuse and a fuse mode determining circuit for determining a fuse-on-mode or a fuse-off-mode for the repair operation of a sub-array block. Consequently, during a repair operation using a conventional laser having a relatively large beam spot, the designated fuse of one fuse group as well as adjacent fuses of a different group may be cut without hindering the repair operation of the sub-array block. Accordingly, increasing the pitch size of the fuses to accommodate the relatively large beam spot of a conventional laser may not be necessary, thus allowing a reduction in the size of the fuse box (and the overall semiconductor memory device). Additionally, the above fuse arrangement may reduce costs by permitting the use of conv…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.