Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same
US7701771B2 · kind B2 · utility
25Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2007 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Mar 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.