Programmable pulsewidth and delay generating circuit for integrated circuits
US7701801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2007 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | May 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.