High-speed serial data receiver architecture
US7702011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2006 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Dec 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.