Buried stress isolation for high-performance CMOS technology

US7704839B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Meikei Ieong · Wappingers Falls, US
• Zhibin Ren · Hopewell Junction, US
• Haizhou Yin · Poughkeepsie, US

Key dates

• Filing date: Apr 8, 2008
• Grant date: Apr 27, 2010
• Expiry date: Jun 14, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.