Inventor · Poughkeepsie, NY, US

Haizhou Yin

173Patents
11h-index
74Co-inventors
79Inventor score

Filing activity: Apr 27, 2005 → Jul 22, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US8043920B2 finFETS and methods of making same Electricity 82 Active
US8835316B2 Transistor with primary and semiconductor spacer, method for manufacturing transistor, and semiconductor chip comprising the transistor Electricity 77 Active
US7547616B2 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics Electricity 26 Active
US8450813B2 Fin transistor structure and method of fabricating the same Electricity 16 Active
US7525162B2 Orientation-optimized PFETS in CMOS devices employing dual stress liners Electricity 15 Active
US7968915B2 Dual stress memorization technique for CMOS application Electricity 15 Active
US8728881B2 Semiconductor device and method for manufacturing the same Electricity 14 Active
US8674449B2 Semiconductor device and method for manufacturing the same Electricity 14 Active
US7834399B2 Dual stress memorization technique for CMOS application Electricity 13 Active
US9087691B2 Method for manufacturing graphene nano-ribbon, mosfet and method for manufacturing the same Performing Operations; Transporting 13 Active
US7525161B2 Strained MOS devices using source/drain epitaxy Electricity 11 Active
US8669155B2 Hybrid channel semiconductor device and method for forming the same Electricity 9 Active
US8803208B2 Method for fabricating contact electrode and semiconductor device Electricity 9 Active
US8410544B2 finFETs and methods of making same Electricity 8 Active
US8642471B2 Semiconductor structure and method for manufacturing the same Electricity 8 Active
US8441050B2 Fin transistor structure and method of fabricating the same Electricity 8 Active
US8105887B2 Inducing stress in CMOS device Electricity 8 Active
US8729638B2 Method for making FINFETs and semiconductor structures formed therefrom Electricity 7 Active
US8198673B2 Asymmetric epitaxy and application thereof Electricity 7 Active
US8546910B2 Semiconductor structure and method for manufacturing the same Electricity 7 Active
US8232178B2 Method for forming a semiconductor device with stressed trench isolation Electricity 6 Active
US7704839B2 Buried stress isolation for high-performance CMOS technology Electricity 6 Active
US7897468B1 Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island Electricity 6 Active
US7396407B2 Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates Electricity 6 Expired
US8587066B2 Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) Electricity 6 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.