Method for fabricating a frontside through-wafer via in a processed wafer and related structure
US7704874B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2006 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Apr 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an exemplary embodiment, a method for fabricating a frontside through-wafer via in a processed wafer includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the processed wafer. The method further includes extending the through-wafer via opening through a substrate to a target depth. The method further includes forming a first conductive layer in the through-wafer via opening and over a through-wafer via pad, which is situated over the at least one interlayer dielectric layer. The first conductive layer in the through-wafer via opening forms an electrical connection between the substrate and the through-wafer via pad. The method further includes forming a second conductive layer on the backside surface of the processed wafer, where the second conductive layer is in electrical contact with the first conductive layer and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.