Annealing to improve edge roughness in semiconductor technology
US7704883B2 · kind B2 · utility
3Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Aug 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.