Semiconductor package substrate
US7705456B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 24, 2008 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Nov 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package substrate includes a main body with a surface having a first circuit layer thereon and a dielectric layer covering the first circuit layer, with a plurality of vias on a portion of the first circuit layer; a plurality of first conductive vias disposed in the vias; a plurality of first electrically connecting pads on the first conductive vias and completely exposed on the dielectric layer having no extending circuits for a semiconductor chip to be mounted thereon, the first electrically connecting pad being electrically connected to the first circuit layer of the first conductive via; and an insulating protective layer disposed on the main body with an opening for completely exposing the first electrically connecting pads, whereby the circuit layout density is increased without disposing circuits between the electrically connecting pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.