Buffer circuit which occupies less area in a semiconductor device
US7705636B2 · kind B2 · utility
1Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2007 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Jan 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018578
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a buffer circuit of a semiconductor memory device, and includes a common bias supply unit and a plurality of interface units having a differential amplifying structure. Each interface unit receives an input signal and differentially amplifies the input signal and a common bias. The common bias supply unit is driven by a reference voltage to provide the common bias signal to each of the interface units. The buffer circuit makes it possible to reduce the area occupied by the buffer circuit in a semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.