Integrated circuit, cell arrangement, method for manufacturing an integrated circuit and for reading a memory cell status, memory module
US7706176B2 · kind B2 · utility
7Cited by
14References
14Claims
0Family size
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Inventor
Key dates
| Filing date | Jan 7, 2008 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Jun 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a cell arrangement is provided. The cell arrangement may include a memory cell and a reference cell. The memory cell has a first memory cell status and a second memory cell status. The reference cell is set to an intermediate memory cell status between the first memory cell status and the second memory cell status.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.