Multi-chip and repairing method based on remaining redundancy cells
US7706198B2 · kind B2 · utility
4Cited by
8References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 26, 2007 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Jul 10, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a repair method of a multi-chip that comprises a plurality of memory chips, each of the memory chips storing information with respect to remaining redundancy cells after repairing at a chip level. The repair method includes testing one of the plurality of memory chips; when the tested memory chip is judged to be defective, checking whether the tested memory chip is repairable, based on the stored information of the remaining redundancy cells; and when the tested memory chip is judged to be repairable, repairing the tested memory chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.