Command buffering for hardware co-simulation
US7707019B1 · kind B1 · utility
9Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2005 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Apr 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of co-simulation involving a high level modeling system and an integrated circuit such as, e.g., a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.