Data processing system, processor and method of data processing having improved branch target address cache

US7707396B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jeffrey Powers Bradford · Rochester, US
• Richard W. Doing · Raleigh, US
• Richard J. Eickemeyer · Rochester, US
• Wael R. El-Essawy · Austin, US
• Douglas R. G. Logan · Austin, US
• Balaram Sinharoy · Poughkeepsie, US
• William E. Speght · Austin, US
• Lixin Zhang · Shenyang, CN

Key dates

• Filing date: Nov 17, 2006
• Grant date: Apr 27, 2010
• Expiry date: Aug 22, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3853
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.