Shared latch for memory test/repair and functional operations
US7707466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2007 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Jun 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a latch component including a first input configured to receive a functional data bit associated with a functional operation, a second input configured to receive a memory test/repair data bit associated with a memory test operation, and a latch comprising a data input and a data output and select logic configured to selectively connect one of the first input or the second input to the data input of the latch based on a mode of operation of the memory device. A method includes operating a memory device in a first mode associated with a memory test operation and in a second mode associated with a functional operation. The method further includes storing a memory test/repair data bit at a latch component of the memory device in the first mode and storing a functional data bit at the latch component in the second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.