System and method for electronic testing of multiple memory devices
US7707468B2 · kind B2 · utility
15Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2007 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Mar 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A testing device may include a memory controller managing a transfer of data; and a plurality of interface boards. Each interface board includes a controller buffer. Each controller buffer transfers data between the memory controller and at least one memory module. The memory controller tests the at least one memory module. The testing device is operable to test the at least one memory module independent of an operating rate of the at least one memory module. The memory controller receives operating data of the at least one memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.