V-shaped multilevel full-chip gridless routing
US7707536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2007 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Sep 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A router organizes an IC area into an array of global routing cells (GRCs) and generates a congestion map providing a separate congestion factor for each GRC boundary. The router then iteratively partitions the IC area into progressively smaller tiles while selecting a route for each net passing between tiles when possible without altering any previously routed net. The router thereafter iteratively merges the tiles into progressively larger tiles while selecting a route for each previously unrouted net residing wholly within a single tile, altering routes of previously routed nets when necessary to accommodate the selected route. When selecting each route for any connection of a net, the router seeks to minimize a cost function of congestion factors of all GRC boundaries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.