Hierarchical 2T-DRAM with self-timed sensing
US7709299B2 · kind B2 · utility
1Cited by
29References
3Claims
0Family size
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Key dates
| Filing date | Aug 27, 2008 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Oct 16, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.