Phase change memory and manufacturing method thereof
US7709822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Dec 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
Both a chalcogenide select device and a chalcogenide memory element are formed within vias within dielectrics. As a result, the chalcogenides is effectively trapped within the vias and no glue or adhesion layer is needed. Moreover, delamination problems are avoided. A lance material is formed within the same via with the memory element. In one embodiment, the lance material is made thinner by virtue of the presence of a sidewall spacer; in another embodiment no sidewall spacer is utilized. A relatively small area of contact between the chalcogenide used to form a memory element and the lance material is achieved by providing a pin hole opening in a dielectric, which separates the chalcogenide and the lance material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.