Memory cell comprising one MOS transistor with an isolated body having an improved read sensitivity
US7709875B2 · kind B2 · utility
4Cited by
4References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 25, 2006 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Mar 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/357
Abstract
A memory cell with one MOS transistor formed in a floating body region isolated on its lower surface by a junction. A region of the same conductivity type as the floating body region but more heavily doped than said region is arranged under the drain region of the MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.