Circuit layout for different performance and method

US7709893B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Florian Bauer · Friedberg, DE
• Christian Pacha · Birkenfeld, DE

Key dates

• Filing date: Jan 31, 2007
• Grant date: May 4, 2010
• Expiry date: May 23, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

A circuit includes a plurality of first MuGFET devices supported by a substrate and having a first performance level. A plurality of second MuGFET devices is supported by the substrate and have a second performance level. The first and second devices in one embodiment are arranged in separate areas that facilitate different processing of the first and second devices to tailor their performance characteristics. In one embodiment, the circuit is an SRAM having pull down transistors with higher performance.