Micro pin grid array with pin motion isolation
US7709968B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2004 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Mar 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.